In reading over Computex coverage I’m impressed by an array of newer, faster computing platforms and storage technologies. At the same time I’m depressed that USB-attached storage is not swimming in this rising tide of increased performance and capability. Simply put: USB ports need more storage bandwidth so they can hold up their end while ushering in a brave new world of performance computing. Let me explain…
Why USB Ports Need More Storage Bandwidth
Thunderbolt 4 tops out at 40 Gbps — that’s a theoretical ceiling of roughly 5 GB/s, and real-world storage transfers run well below that. It was impressive when it arrived. It isn’t anymore. Thunderbolt 5 moved the needle, pushing up to 120 Gbps on the read side and 40 Gbps on writes. Indeed, its asymmetric bandwidth design delivers somewhere in the neighborhood of 6–7 GB/s of actual storage throughput under optimal conditions.
That’s a real boost, and to give credit where it’s due: Intel’s Thunderbolt 5 is the current high-water mark for USB-attached external storage performance. But here’s the problem — “high-water mark for external” and “keeping pace with internal” are two very different things. Alas, the gap between them is widening fast.
Phison’s PCIe 5 Controllers: Lapping the Field
Let’s talk about what’s happening inside the box right now. Phison’s E26 controller — the flagship PCIe 5.0 x4 part — pushes sequential reads up to roughly 14 GB/s and writes near 12 GB/s. That’s not a roadmap promise. That’s shipping silicon, today, in drives like the Crucial T705 and Seagate FireCuda 540. And the reason those numbers are possible is that PCIe 5.0 x4 delivers approximately 32 GB/s of raw bus bandwidth — a figure Thunderbolt 5’s best-case scenario can’t remotely approach.
I’ll be blunt: Thunderbolt 5 running at its theoretical maximum is still less than a quarter of PCIe 5’s available bus bandwidth. External storage users are working with a narrow pipe while internal NVMe users are drinking from a fire hose. And here’s what makes it even more galling — PCIe 5 SSDs themselves are already hitting their ceiling and looking nervously at what comes next. The interface they’re starved for is PCIe 6, which is already coming down the pipe.
Phison PCIe 6 Controllers: Next Tier Is Here
Computex 2025 was where Phison first made the PCIe 6.0 future feel real, and the momentum has only built from there. The next-generation Phison controller roadmap targets PCIe 6.0 x4 — an interface that theoretically delivers around 64 GB/s of raw bandwidth per slot, thanks to PAM4 signaling running at 64 GT/s per lane. Real-world sequential read targets are north of 20 GB/s.
Think about what that means for Thunderbolt 5’s ceiling. A single PCIe 6 SSD — one drive, one M.2 slot — could in principle saturate nearly five simultaneous Thunderbolt 5 connections running flat out. The Thunderbolt bandwidth ceiling doesn’t just look inadequate at that point; it looks comical. External storage users are so far behind that “catching up” is a massive understatement. Instead, designs must condider a completely different approach.
What Needs to Change?
USB4 Gen 3×2 sits at 40 Gbps — identical to Thunderbolt 4, still not enough. USB4 v2 bumps that to 80 Gbps, which helps at the margins but still lands less than a third of PCIe 5’s bus bandwidth, let alone PCIe 6’s. These are incremental improvements on an interface that needs a fundamental rethink, not a spec bump.
The industry needs a paradigm shift. Either Thunderbolt 6 or USB5 — whatever we end up calling it — must arrive with dramatically higher bandwidth, we’re talking 200+ Gbps as a floor, not a ceiling. Alternatively, PCIe tunneling over external cables needs to mature to the point where it can fully exploit NVMe speeds without overhead that kills performance today. One or the other. Probably both, eventually.
Until one of those paths becomes real and shipping, external storage users are locked in a performance ghetto. Internal SSD buyers are sprinting ahead with every product generation. The storage industry owes external storage users a credible, substantive answer. I’m not talking about another incremental spec revision, not another narrowly defined workaround. Computex 2026 is the right venue and this is the right moment. USB silicon designers need to envision, then deliver something worth getting excited about. So far, I can’t see it. Let’s hope for something amazing, shall we?
